Integrated circuit ("IC") chips often include circuits that must respond within a desired time window upon receipt of a clock signal. For example, a memory IC chip may include a plurality of memory cells arranged in rows and columns, with sense amplifiers coupled between complementary column bit line pairs. Upon receipt of a sense enable signal, the sense amplifiers are enabled and must develop and provide the true state of the memory cell being read as a latched output signal. This sense enable signal can be a delayed version of an input clock signal. If the time delay is too short and the sense amplifiers are enabled too soon, the true stored value cannot be reliably read under all circumstances. If the sense amplifiers are enabled too late, access and system cycle times are delayed, time is wasted, and the monetary value of the IC containing the sense amplifiers can be diminished.
Using simulation techniques, an initial anticipated timing delay is determined for the prototype fabrication of a given IC design. In practice, determining the precise amount of delay required for an IC chip is not always easy to discern. More specifically, semiconductor process variations, defects, and system offsets can inject uncertainty into predicting the required delay. After fabrication, prototype wafers are thoroughly characterized by extensive testing under extreme timing and environmental conditions, and the actual nominal desired delay can generally be approximated.
Based on the characterization results, the subsequent production masks can be altered to permanently provide an amount of delay that hopefully is sufficiently close to the actual nominal desired delay for mass production. The prior art attempts to so provide the proper delay by modifying only the metallization. However, often other layers must also be modified to produce a time delay closer to the desired value determined by characterization.
But although all sense amplifiers on all wafers are subjected to the same metallization-fixed delay, the actual required delay may differ among the fabricated sense amplifiers. Ideally, all memory cells fabricated on different wafers should be equally fast in generating adequate signals to the sense amplifier inputs for reliable sensing with an optimally delayed latch signal. However, fabrication process variations, semiconductor defects and system offsets exist. Some defects are sufficiently severe that the chip cannot be salvaged, e.g., a Vcc-to-ground short. However, a statistically significant number of defects merely slow the generation of proper signals, e.g., the time required to generate sufficient signal from a memory cell onto the associated bit lines.
These variables can result in some individual IC chips having one or more sense amplifiers that will function correctly, but at a slower speed than the bulk of the sense amplifiers located elsewhere on that chip. Faster responding ICs are potentially more valuable than the slower responding ICs, and can generally be sold for a higher price. Although the slower responding ICs can still be used in applications permitting a longer delay between latch signal input and sense amplifier output, such ICs may command a lower sales price.
The prior art metallization pattern technique for fixing delay is relatively inflexible and does not permit customizing the delay after IC fabrication is complete. If the metallization-fixed delay is too short, IC chips containing defectively slow but still functional sense amplifiers may be enabled too soon. As such, these sense amplifiers would not provide a proper output signal, and the IC would therefore not be functional. In the prior art, such IC chips generally cannot be salvaged. However, if the delay could be increased after fabrication, a significant number of these chips could still be functional, albeit at a slower speed.
Further, while prior art techniques may provide an appropriate nominal delay for some of the sense amplifiers on some of the IC chips, this delay may be unnecessarily long for sense amplifiers on other identical chips. Thus, although these other sense amplifiers would be fully functional with a shorter time delay, they nonetheless are compelled to operate with an unnecessarily long nominal delay. These under-utilized chips must then be sold for a smaller price than if they could be operated at a reduced delay time. In essence, the prior art delay technique must sacrifice yield, speed, or both.
What is needed is a test mode method for ascertaining actual optimum delay for a fabricated IC on a per chip basis. Such delay should then be individually programmable with an acceptable degree of delay resolution, again on a per-IC chip basis after fabrication is complete. So doing would permit post-fabrication customization of the time delay to meet the needs of the faster, defect-free chips by providing shorter delays, yielding IC chips with faster access times. Further, such method would permit extending the delay to maintain functionality of slower IC chips that may contain small defects that delay sensing or generation of a read signal.
The present invention provides such a method and system that satisfies these needs.